• Design and FPGA Implementation...

Result: Design and FPGA Implementation of 8-Bit Vedic Multiplier Using Hybrid Adder

Title:
Design and FPGA Implementation of 8-Bit Vedic Multiplier Using Hybrid Adder
Authors:
Datta, DebarshiAff1, IDs4000902501878x_cor1, Naskar, Mrinal Kanti
Source:
National Academy Science Letters. :1-4
Database:
Springer Nature Journals