American Psychological Association 6th edition

Datta, D., & Naskar, M. K. (2025). Design and FPGA Implementation of 8-Bit Vedic Multiplier Using Hybrid Adder. National Academy Science Letters, 1-4. https://doi.org/10.1007/s40009-025-01878-x

ISO-690 (author-date, English)

DATTA, Debarshi and NASKAR, Mrinal Kanti, 2025. Design and FPGA Implementation of 8-Bit Vedic Multiplier Using Hybrid Adder. National Academy Science Letters. 3 December 2025. P. 1-4. DOI 10.1007/s40009-025-01878-x.

Modern Language Association 9th edition

Datta, D., and M. K. Naskar. “Design and FPGA Implementation of 8-Bit Vedic Multiplier Using Hybrid Adder”. National Academy Science Letters, Dec. 2025, pp. 1-4, https://doi.org/10.1007/s40009-025-01878-x.

Mohr Siebeck - Recht (Deutsch - Österreich)

Datta, Debarshi/Naskar, Mrinal Kanti: Design and FPGA Implementation of 8-Bit Vedic Multiplier Using Hybrid Adder, National Academy Science Letters 2025, 1-4.

Emerald - Harvard

Datta, D. and Naskar, M.K. (2025), “Design and FPGA Implementation of 8-Bit Vedic Multiplier Using Hybrid Adder”, National Academy Science Letters, pp. 1-4.

Warning: These citations may not always be 100% accurate.