American Psychological Association 6th edition

Malhotra, G., Duraiswamy, P., & Kishore, J. K. (2023). FPGA Accelerated Parallel Hs Clone GA for Digital Circuit Configuration in CGP Format. Journal of The Institution of Engineers (India): Series B: Electrical, Electronics & Telecommunication and Computer Engineering, 104(5), 1079-1089. https://doi.org/10.1007/s40031-023-00918-8

ISO-690 (author-date, English)

MALHOTRA, Gayatri, DURAISWAMY, Punithavathi und KISHORE, J. K., 2023. FPGA Accelerated Parallel Hs Clone GA for Digital Circuit Configuration in CGP Format. Journal of The Institution of Engineers (India): Series B: Electrical, Electronics & Telecommunication and Computer Engineering. 1 Oktober 2023. Vol. 104, no. 5, p. 1079-1089. DOI 10.1007/s40031-023-00918-8.

Modern Language Association 9th edition

Malhotra, G., P. Duraiswamy, und J. K. Kishore. „FPGA Accelerated Parallel Hs Clone GA for Digital Circuit Configuration in CGP Format“. Journal of The Institution of Engineers (India): Series B: Electrical, Electronics & Telecommunication and Computer Engineering, Bd. 104, Nr. 5, Oktober 2023, S. 1079-8, https://doi.org/10.1007/s40031-023-00918-8.

Mohr Siebeck - Recht (Deutsch - Österreich)

Malhotra, Gayatri/Duraiswamy, Punithavathi/Kishore, J. K.: FPGA Accelerated Parallel Hs Clone GA for Digital Circuit Configuration in CGP Format, Journal of The Institution of Engineers (India): Series B: Electrical, Electronics & Telecommunication and Computer Engineering 2023, 1079-1089.

Emerald - Harvard

Malhotra, G., Duraiswamy, P. und Kishore, J.K. (2023), „FPGA Accelerated Parallel Hs Clone GA for Digital Circuit Configuration in CGP Format“, Journal of The Institution of Engineers (India): Series B: Electrical, Electronics & Telecommunication and Computer Engineering, Vol. 104 No. 5, S. 1079-1089.

Achtung: Diese Zitate sind unter Umständen nicht zu 100% korrekt.