Result: Hardware design of a FPGA-based synchronizer for Hiperlan/2
Title:
Hardware design of a FPGA-based synchronizer for Hiperlan/2
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :494-504
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 12 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Circuit numérique, Digital circuit, Circuito numérico, Conception circuit, Circuit design, Diseño circuito, Emetteur récepteur, Transceiver, Emisor receptor, Méthode domaine temps fréquence, Time frequency domain method, Método dominio tiempo frecuencia, Point fixe, Fix point, Punto fijo, Réseau porte programmable, Field programmable gate array, Red puerta programable, Synchronisateur, Synchronizer, Sincronizador, Synchronisation, Synchronization, Sincronización, Taux erreur bit, Bit error rate, Tasa error bit
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
Dpto. Ingenieria Electrónica, Universidad Politécnica de Valencia, Gandia, Spain
Dpto. Física y Arquitectura Computadores, Universidad Miguel Hernández, Elche, Spain
Dpto. Comunicaciones, Universidad Politécnica de Valencia, Gandia, Spain
Dpto. Física y Arquitectura Computadores, Universidad Miguel Hernández, Elche, Spain
Dpto. Comunicaciones, Universidad Politécnica de Valencia, Gandia, Spain
ISSN:
0302-9743
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems
Electronics
Electronics
Accession Number:
edscal.16107575
Database:
PASCAL Archive
Further Information
This paper deals with the design and implementation of a frame, time and frequency synchronizer for Hiperlan/2 WLAN standard. In a packet oriented system, to perform a quick and correct synchronization it is critical to avoid severe bit error rate degradation. So, the design of this subsystem is one of the most challenging tasks to be done in the implementation of a transceiver. In this paper we give practical solutions to the hardware design problems that arise when the synchronization algorithm is turned into a digital circuit. We evaluate the fixed-point realization of the synchronization algorithm and introduce some simplifications to reduce, as much as possible, the cost in area of the circuit without losing its performance.