Result: A dynamically reconfigurable asynchronous FPGA architecture

Title:
A dynamically reconfigurable asynchronous FPGA architecture
Authors:
XIN JIA, RAJAGOPALAN, Jayanthi, VEMURI, Ranga
Source:
FPL 2004 : field-programmable logic and applications (Antwerp, 30 August - 1 September 2004)Lecture notes in computer science. :836-841
Publisher Information:
Berlin: Springer, 2004.
Publication Year:
2004
Physical Description:
print, 11 ref
Original Material:
INIST-CNRS
Subject Terms:
Computer science, Informatique, Mathematics, Mathématiques, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Informatique; automatique theorique; systemes, Computer science; control theory; systems, Logiciel, Software, Traitement des langages et microprogrammation, Language processing and microprogramming, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Circuits intégrés par fonction (dont mémoires et processeurs), Integrated circuits by function (including memories and processors), Architecture reconfigurable, Reconfigurable architectures, Conception circuit, Circuit design, Diseño circuito, Réseau logique programmable, Programmable logic array, Red lógica programable, Réseau porte programmable, Field programmable gate array, Red puerta programable, Système temporisé, Timed system, Sistema temporizado, Transmission asynchrone, Asynchronous transmission, Transmisión asincrónica, Globalement asynchrone localement synchrone, Globally asynchronous locally synchronous, Globalmente asincrono localmente sincrono
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
University of Cincinnati, United States
ISSN:
0302-9743
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=16107586
Rights:
Copyright 2004 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Computer science; theoretical automation; systems

Electronics
Accession Number:
edscal.16107586
Database:
PASCAL Archive

Further Information

This paper presents APL, an Asynchronous Programmable Logic array, as a flexible dynamically reconfigurable multi-application platform with self-reconfigurability. APL employs a Globally-Asynchronous-Locally-Synchronous (GALS) architecture. It consists of Timing Regions (TRs) which operate independently under locally generated clocks and communicate with each other through handshaking asynchronous interfaces. Different applications are mapped into different TRs, so they can run independently. And because of the asynchronous communication, dynamic partial reconfiguration is easily realized with TRs as the basic reconfiguration units. Self-reconfiguration is realized by giving each TR the capability to access the central configuration controller which, in turn, can read/write the configuration memory.