• 3-D silicon integration and si...

Result: 3-D silicon integration and silicon packaging technology using silicon through-vias

Title:
3-D silicon integration and silicon packaging technology using silicon through-vias
Authors:
KNICKERBOCKER, John U, PATEL, Chirag S, COTTE, John M, ANDRY, Paul S, TSANG, Cornelia K, PAIVIKKI BUCHWALTER, L, SPROGIS, Edmund J, HUA GAN, HORTON, Raymond R, POLASTRE, Robert J, WRIGHT, Steven L
Source:
2005 Custom Integrated Circuits ConferenceIEEE journal of solid-state circuits. 41(8):1718-1725
Publisher Information:
New York, NY: Institute of Electrical and Electronics Engineers, 2006.
Publication Year:
2006
Physical Description:
print, 22 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Circuits intégrés, Integrated circuits, Conception. Technologies. Analyse fonctionnement. Essais, Design. Technologies. Operation analysis. Testing, Dispositifs diélectriques et dispositifs à base de verre et de solides amorphes, Dielectric, amorphous and glass solid devices, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Circuits électriques, optiques et optoélectroniques, Electric, optical and optoelectronic circuits, Propriétés des circuits, Circuit properties, Circuits optiques et optoélectroniques, Optical and optoelectronic circuits, Optoélectronique intégrée. Circuits optoélectroniques, Integrated optoelectronics. Optoelectronic circuits, Circuit intégré, Integrated circuit, Circuito integrado, Condensateur, Capacitor, Condensador, Câblage, Wiring, Colocación cables, Découplage, Decoupling, Desacoplamiento, Emetteur récepteur, Transceiver, Emisor receptor, Encapsulation céramique, Ceramic packaging, Encapsulación cerámica, Evaluation performance, Performance evaluation, Evaluación prestación, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Haute performance, High performance, Alto rendimiento, Interconnexion, Interconnection, Interconexión, Lithographie, Lithography, Litografía, Matrice formage, Die, Matriz formadora, Module multipuce, Multichip module, Modulo multipulga, Modèle 2 dimensions, Two dimensional model, Modelo 2 dimensiones, Optoélectronique, Optoelectronics, Optoelectrónica, Packaging électronique, Electronic packaging, Packaging electrónico, Pastille électronique, Wafer, Pastilla electrónica, Structure 3 dimensions, Three dimensional structure, Estructura 3 dimensiones, Système sur puce, System on a chip, Sistema sobre pastilla, Technologie MOS complémentaire, Complementary MOS technology, Tecnología MOS complementario, Système sur boîtier, System on package, Sistema sobre estuche, 3-D, Chip integration, high bandwidth, integrated decoupling capacitors, interconnection, silicon packaging, silicon through-vias
Document Type:
Conference Conference Paper
File Description:
text
Language:
English
Author Affiliations:
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, United States
IBM T. J. Watson Research Center, Essex Junction, VT 05452, United States
IBM T. J. Watson Research Center, Hopewell Junction, NY 12533, United States
ISSN:
0018-9200
Access URL:
http://pascal-francis.inist.fr/vibad/index.php?action=search&terms=18032567
Rights:
Copyright 2006 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Accession Number:
edscal.18032567
Database:
PASCAL Archive

Further Information

System-on-Chip (SOC) and System-on-Package (SOP) technologies each have advantages depending on application needs. As system architects and designers leverage ever-increasing CMOS technology densities, a range of two- and three-dimensional silicon integration technologies are emerging which will likely support next-generation high-volume electronic applications and may serve high-performance computing applications. This paper will discuss a few emerging technologies which offer opportunities for enhanced circuit performance, or reduced power as one example. Silicon-on-silicon integration may include three-dimensional (3-D) integration on-chip or may leverage chip stacking or chip integration on package. Common technology features include silicon through-vias, high-I/O interconnection and silicon-on-silicon either as 3-D integrated circuits, integrated chip stacks or silicon-on-silicon packages with passive function or high-bandwidth wiring. Silicon chips on silicon interposers with integrated function such as decoupling capacitors may provide a better module architecture compared to increased on-chip decoupling or off chip discrete capacitors mounted on package at the chip perimeter or underside of the package. Advanced silicon carrier package technology with fine pitch (50 μm) interconnection is described. This silicon carrier package contains silicon through-vias and offers > 16 x increase over standard chip I/O, a 20 x to 100 × increase in wiring density over traditional organic and ceramic packaging, and allows for integrated high-performance passives. Silicon carrier technology supports lithographic scaling and provides a basis for known good die (KGD) wafer testing. It may be considered for use in a number of applications including optoelectronic (OE) transceivers, silicon interposers with integrated decoupling capacitors, and mini-multi-chip modules (MMCMs) which integrate heterogeneous dies forming a single virtual chip.