Result: 1.2 nm capacitance equivalent thickness gate stacks on Si-passivated GaAs
Title:
1.2 nm capacitance equivalent thickness gate stacks on Si-passivated GaAs
Authors:
Source:
Microelectronic engineering. 88(7):1066-1069
Publisher Information:
Amsterdam: Elsevier, 2011.
Publication Year:
2011
Physical Description:
print, 16 ref
Original Material:
INIST-CNRS
Subject Terms:
Electronics, Electronique, Sciences exactes et technologie, Exact sciences and technology, Physique, Physics, Domaines interdisciplinaires: science des materiaux; rheologie, Cross-disciplinary physics: materials science; rheology, Science des matériaux, Materials science, Méthodes de dépôt de films et de revêtements; croissance de films et épitaxie, Methods of deposition of films and coatings; film growth and epitaxy, Epitaxie par faisceaux chimiques, ioniques, atomiques et moléculaires, Molecular, atomic, ion, and chemical beam epitaxy, Sciences appliquees, Applied sciences, Electronique, Electronics, Electronique des semiconducteurs. Microélectronique. Optoélectronique. Dispositifs à l'état solide, Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices, Dispositifs diélectriques et dispositifs à base de verre et de solides amorphes, Dielectric, amorphous and glass solid devices, Fabrication microélectronique (technologie des matériaux et des surfaces), Microelectronic fabrication (materials and surfaces technology), Metaux. Metallurgie, Metals. Metallurgy, Corrosion, Mécanismes fondamentaux et formes de la corrosion, Corrosion mechanisms, Composé IV-VI, IV-VI compound, Compuesto IV-VI, Capacité électrique, Capacitance, Capacitancia, Condensateur MOS, MOS capacitor, Capacidad MOS, Couche interfaciale, Interfacial layer, Capa interfacial, Epaisseur, Thickness, Espesor, Dicke, Epitaxie jet moléculaire, Molecular beam epitaxy, Fabrication microélectronique, Microelectronic fabrication, Fabricación microeléctrica, Grille transistor, Transistor gate, Rejilla transistor, Matériau amorphe, Amorphous material, Material amorfo, Mesure électrique, Electrical measurement, Medida eléctrica, Elektrisches Messen, Multicouche, Multiple layer, Capa múltiple, Mehrfachschicht, Oxydation, Oxidation, Oxidación, Oxyde d'hafnium, Hafnium oxide, Hafnio óxido, Hafniumoxid, Oxyde de silicium, Silicon oxides, Passivation, Pasivación, Passivierung, Spectre photoélectron RX, X-ray photoelectron spectra, Traitement thermique, Heat treatment, Tratamiento térmico, Waermebehandlung, 8540H, HfO2, SiO2, Amorphous Si, CET, GaAs passivation, Hf02, MBE, MOSCAP, XPS
Document Type:
Conference
Conference Paper
File Description:
text
Language:
English
Author Affiliations:
IBM Research - Zurich, Säumerstrasse 4, 8803 Rüschlikon, Switzerland
ISSN:
0167-9317
Rights:
Copyright 2015 INIST-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
CC BY 4.0
Sauf mention contraire ci-dessus, le contenu de cette notice bibliographique peut être utilisé dans le cadre d’une licence CC BY 4.0 Inist-CNRS / Unless otherwise stated above, the content of this bibliographic record may be used under a CC BY 4.0 licence by Inist-CNRS / A menos que se haya señalado antes, el contenido de este registro bibliográfico puede ser utilizado al amparo de una licencia CC BY 4.0 Inist-CNRS
Notes:
Electronics
Metals. Metallurgy
Physics and materials science
Metals. Metallurgy
Physics and materials science
Accession Number:
edscal.24284416
Database:
PASCAL Archive
Further Information
Experiments to increase the specific capacitance of MOS capacitors consisting of HfO2 on a passivating interfacial layer (IL) of amorphous Si (a-Si) on GaAs are described. XPS analysis of the layers and electrical measurements on the capacitors are combined to study the evolution of the gate stack during deposition and subsequent heat treatments. It is shown that oxidation of the a-Si IL is a major factor in preventing the attainment of a scaled capacitance equivalent thickness (CET). By controlling the deposition of the layers, the gate metal and the heat treatments, a highly scaled gate stack with a CET of 1.2 nm and a leakage reduction of more than 4 orders of magnitude with respect to SiO2/Si was realized. .