LEE, C.-C., LEE, C.-C., KU, H.-T., CHANG, S.-M., & CHIANG, K.-N. (2007, January 1). Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology. 47(2-3). Oxford: Elsevier, 2007. Retrieved from http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18518713
ISO-690 (author-date, English)LEE, Chang-Chun, LEE, Chien-Chen, KU, Hsiao-Tung, CHANG, Shu-Ming and CHIANG, Kuo-Ning, 2007. Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology. In: [online]. Oxford: Elsevier, 2007. 1 January 2007. Available from: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18518713
Modern Language Association 9th editionLEE, C.-C., C.-C. LEE, H.-T. KU, S.-M. CHANG, and K.-N. CHIANG. Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology. no. 2-3, Oxford: Elsevier, 2007., 2007, http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18518713.
Mohr Siebeck - Recht (Deutsch - Österreich)Emerald - Harvard
LEE, C.-C., LEE, C.-C., KU, H.-T., CHANG, S.-M. and CHIANG, K.-N. (2007), “Solder joints layout design and reliability enhancements of wafer level packaging using response surface methodology”, in , Vol. 47, Oxford: Elsevier, 2007., available at: http://pascal-francis.inist.fr/vibad ndex.php?action=search&terms=18518713.